Acquisition for GPS receivers: An investigation of parallelism for FPGA implementation

This project has investigated parallelism in the
fields of GPS receivers and FPGA architectures.
The project problem was to test if it is possible
to design a GPS acquisition block for
an FPGA, with the timing requirement that it
should be able to execute in less than 1 millisecond.
The tool for the project was to use
parallelism to find a trade-off between execution
time and the required area in the FPGA,
so the design would meet the timing demands.
An algorithm, based on the serial search algorithm,
where designed and implemented, using
the system-level tool Xilinx System Generator.
A model executing 32 blocks in parallel was
developed and name Mode32.
Mode32 meets the timing and resource demands
set for the project, but unfortunately
there were some timing issues in the model, so
it has not been tested with other than known
test data.
In the project, additional models for the acquisition
block were also designed, implemented
and tested. The models were a C/A code generator
and a carrier generator. Both models
tests were successful.
Finally a design ideas are presented for a complete
design for a GPS Acquisition block for
FPGA implementation.